package XunChunCPU.MEM

import chisel3._
import XunChunCPU.common.CommonConfig._ 
import XunChunCPU.common.Bundles._


class MEMReg extends Module{
    val io = IO(new Bundle {
        val memInfo_in = Flipped(new MemInfo)
        val memInfo_out = new MemInfo
        val wbInfo_in = Flipped(new WBInfo)
        val wbInfo_out = new WBInfo
        val valid_in = Input(Bool())
    })
    val memType = RegInit(4.U(3.W))
    val memAddr = RegInit(0.U(32.W))
    val memData = RegInit(0.U(32.W))
    val regwe = RegInit(false.B)
    val regAddr = RegInit(0.U(5.W))
    val wData = RegInit(0.U(32.W))

    when(io.valid_in){
        memType := io.memInfo_in.memType
        memAddr := io.memInfo_in.memAddr
        regwe := io.wbInfo_in.regwe
        regAddr := io.wbInfo_in.regAddr
        wData := io.wbInfo_in.wData 
    }.otherwise{
        memType := MemNothing
        memAddr := 0x80400000L.U
        regwe := false.B
        regAddr := 0.U
        wData := 0.U
    }


    io.memInfo_out.memAddr := memAddr
    io.memInfo_out.memType := memType
    io.wbInfo_out.regAddr := regAddr
    io.wbInfo_out.regwe := regwe
    io.wbInfo_out.wData := wData
}